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1/28 AN1261 application note december 2001 bcd off-line technology the high level of integration of the l6590 family is made possible by the bcd off-line technology. compared to other high voltage technolog ies, bcd allows more design flexibil ity due to the large variety of components available: n high voltage n-channel ldmos (700v) n medium voltage bipolar transistor (20v, both npn and pnp type) n low and medium voltage cmos devices (5 to 10v) n zener voltage references n resistors and capacitors. figure 1. bcd off-line cross sections cmos poly1 - poly2 cap pch. nch. h.v. ldmos l.v. ldmos npn lpnp ds gd gbecbce d gdgs s s by claudio adragna getting familiar with the l6590 family high-voltage fully integrated power supply in offline switchers in general and in low power ones in particular, the driving factors when making a design are reduction of cost, component count, size, weight as well as design to market. the monolithic or oone-chipo solution, where pwm control and power switch are integrated on the same sil- icon and/or housed in the same package, looks very attractive especially in low power applications, where the typical approach, with separate pwm ic and power switch, features the higher cost-per-watt. a mono- lithic solution, which allows to build an smps with very few external parts, has in this case a dramatic impact. on the other hand, the flexibility of the otwo-chipo approach does not provide significant advantages in such systems where no sophisticated functionality is normally required. additionally, the monolithic approach im- proves system reliability and reduces design effort. this application note describes in details the l6590 and the l6590a, a set of integrated monolithic switching regulators for offline converters. after a brief description of bcd offline, the technology used for these devices, their internal architecture and functionality will be described in details, then a number of application ideas and application examples will be provided.
AN1261 application note 2/28 in this way it is possible to realize compact and robust design solutions by integrating on the same silicon chip both high voltage power components and sophisticated control and protection functions . standard junction isolation is used, as shown in the cross section of the technology in figure 1. the waste of silicon area due to lateral diffusion in thick epitaxial layers, normally required for high voltage capability, is elim- inated with the so-called resurf (reduced surface field) approach. this technique allows the ic to withstand high voltages in very thin epitaxial layers ( 10 m m). the resurf approach implies lateral current flow in the high voltage dmos, so this device has a lateral struc- ture. as a result, the substrate of the ic is grounded and there is much less noise generation compared to a discrete fet. general device description this family is a set of monolithic switching regulators able to operate with a very wide range of input voltage and primarily intended for flyback, boost or forward topologies in offline applications. the power that the devices are able to handle is in excess of 10w in 110vac or wide range mains (wrm) applications and from 15 to 20w in 220vac mains applications. in this power range flyback is the most common topology, so it will be considered as the reference topology in the following. the family includes three members: the l6590 (housed in minidip), the l6590d (housed in so16w) and the l6590a (housed in minidip). typically, the l6590 and the l6590d are suitable for low-power ac-dc adapters, auxiliary power suppli es of crt and lcd monitors and tv's. the l6590a may be used in these applica tions as well, however it is more specific for auxiliary power supplies of desktop pc's and servers. all of the devices can be used also to build both high-voltage and low- voltage dc-dc converters since they are able to operate with input voltages as low as 40v . figure 2. l6590 family internal block diagram figure 2 shows the internal block diagrams of the devices. the internal power switch is realised with a lateral high voltage power mosfet with a typical r ds(on) of 13 w and a v (br)dss of 700v. the fixed frequency (65 khz) internal oscillator and the non-dissipative start-up allow to minimize the external components count. the pwm control incorporates a voltage mode control scheme and converter's output voltage regulation can be achieved with both opto-isolated and primary sensing feedback. internal protections like cycle-by-cycle current supply & u vlo ovp ocp + - + - 2.5v + - drain (1) [1] v cc (3) [4] bok [6] comp (4) [7] gnd (6,7,8) pgnd [9, ..., 16] vref br ownout pw m standby start-up osc 65/22 khz thermal shutdown 2.5v - + vfb (5) [8] vref sgnd [5] [x] : l6590d (so16w) supply & uvlo over voltage over cu rrent + - + - 2.5v + - drain (1) vcc (3) bok (5) comp (4) gnd (6,7,8) vre f 1ma brownout pw m standby start-up osc 65/22 khz thermal s.dow n l6590/l6590d l6590a
AN1261 application note 3/28 limiting, output overvoltage protection, mains undervoltage (brownout) protection and thermal shutdown gener- ate robust design solutions. an outstanding feature of the converters based on the l6590 family is their very low consumption under no-load conditions. the low operating current and low parasitics of the devices, as well as their standby function, which automatically reduces the oscillator frequency from 65khz to 22khz under light load conditions, allow to accom- plish with regulations on standby consumption from the mains, such as blue angel or others. pin connections and description the l6590 and l6590a are housed in minidip package for through-hole assembly, while the l6590d is housed in so16w package for smd assembly. devices' pinout in both package versions is shown in figure 3. table 1 summarises briefly pin functionality. figure 3. l6590 family pin connections table 1. l6590 family pin connections pin # name description l6590 l6590a l6590d 1 1 drain drain connection of the internal power mosfet. the internal high volt- age start-up generator sinks current from this pin. 2 2, 3 n.c. not internally connected. provision for clearance on the pcb. 34v cc supply pin of the ic. an electrolytic capacitor is connected between this pin and ground. the internal start-up generator charges the capacitor until the voltage reaches the start-up threshold. the pwm is stopped if the voltage at the pin exceeds a certain value. 4 4 comp output of the error amplifier. used for control loop compensation or to directly control pwm with an optocoupler. 5-8vfb inverting input of the error amplifier. the non-inverting one is internally connected to a 2.5v 2% reference. this pin can be grounded in some feedback schemes. 6to8 - gnd connection of both the source of the internal mosfet and the return of the bias current of the ic. pins connected to the metal frame to facilitate heat dissipation. - 5 6 bok brownout protection. if the voltage applied to this pin is lower than 2.5v the pwm is disabled. this pin is typically used for sensing the input volt- age of the converter through a resistor divider. if not used, the pin can be either left floating or connected to vcc through a 15 k w resistor. - - 5 sgnd current return for the bias current of the ic. - - 9 to 16 pgnd connection of the source of the internal mosfet. pins connected to the metal frame to facilitate heat dissipation. vfb drain n.c. vcc comp vfb gnd gnd gnd minidip l6590 drain n.c. n.c. vcc sgnd bok comp vfb pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd so16w l6590d bok drain n.c. vcc comp gnd gnd gnd minidip l6590a
AN1261 application note 4/28 the l6590 is provided with an error amplifier for both primary and opto-isolated feedback; the l6590a, specific for pc auxiliary smps, has brownout protection on board in place of the error amplifier, thus it is eligible for opto-isolated feedback. both the error amplifier and brownout protection are available in the smd version l6590d. thermal properties all of the ground pins (6, 7 and 8 in minidip, 9 to16 in so16w) are internally connected to the copper frame in order for heat to be easily removed from the silicon die. an heatsink can then be realized by simply making pro- vision of some cm 2 of copper on the pcb. figure 4 shows the junction-to-ambient thermal resistance achievable with both packages as a function of the dissipating copper area on the pcb. the junction-to-pin thermal resistance is estimated about 15 c/w in the minidip package and about 20 c/w in the so16w. figure 4. l6590 family packages junction-to-ambient thermal resistance detailed functions description in the following sections the various functional blocks shown in fig. 2 as well as the most important internal func- tions will be described in details. start-up circuit and internal supply when power is first applied to the circuit the voltage on the bulk capacitor builds up and, as it reaches some ten volts, an internal high-voltage current generator is sufficiently biased to start operating. it draws about 4.5ma from the input bulk capacitor through the primary winding of the transformer and the drain pin. this current charges the capacitor connected between pin v cc (3) and ground, making its voltage rise linearly. as the vcc voltage reaches the start-up threshold (14.5v typ.) the chip, after resetting all its internal logic, starts operating, the internal power mosfet is enabled to switch and the internal high-voltage generator is discon- nected. the ic is powered by the energy stored in the v cc capacitor until the self-supply circuit (typically an auxiliary winding of the transformer) develops a voltage high enough to sustain the operation. this start-up se- quence is summarised in figure 5. 0.5 1 1.5 2 2.5 3 3.5 4 4.5 [cm^2] 47 48 49 50 51 52 53 54 55 56 [ c/w] 1oz 2oz pdiss = 1.4 w so16w rthja vs. pcb copper area 0.5 1 1.5 2 2.5 3 3.5 4 4.5 [cm^2] 46 47 48 49 50 51 52 [ c/w] 1oz 2oz pdiss = 1.4 w minidip rthja vs. pcb copper area
5/28 AN1261 application note figure 5. start-up sequence figure 6 shows the internal schematic of the high-voltage start-up generator. it is made up of a high-voltage n- channel fet whose gate is biased by a 15m w resistor. if the v cc voltage is below the start-up threshold, the uvlo signal is low and the high-voltage fet is biased above its threshold as the drain voltage is high enough. the drain current is controlled and held constant by the negative feedback loop including the 150 w resistor and the bjt. as the v cc voltage reaches the start-up threshold the uvlo signal goes high, the small fet is turned on and the high voltage fet is cut off. the two diodes prevent reverse flow current that would otherwise occur as the drain, during the on-state of the power fet, has a voltage below v cc . the residual consumption of this circuit is just the one on the 15m w resistor ( 10 mw at 400vdc), typically 50-70 times lower, under the same conditions, compared to a standard start-up circuit made with an external dropping resistor. as the ic is running, the supply voltage, typically generated by a self-supply winding, can range between the overvoltage protection limit (ovp, see the relevant section) and the threshold of the undervoltage lockout (uv- lo). below this value the device is switched off and the internal start-up generator is activated. the two thresh- olds are in tracking. the voltage on the v cc pin is limited at safe values by a zener diode. its breakdown voltage tracks the over- voltage protection threshold. the internal supply architecture is illustrated in figure 7. the v cc voltage is monitored by the uvlo block which turns the device off if it falls below the uvlo threshold and is directly used to supply the driver of the power mosfet. from the v cc bus it is derived the bandgap reference, internally trimmed and temperature compen- sated, used to generate the 2.5v reference for the error amplifier (not in the l6590a). also this reference volt- age is monitored by the uvlo block and the device is stopped if the value is not within the spec. the 2.5v reference is also used for the linear regulator that provides the two 5v internal buses supplying the analog part and the digital part of the ic respectively. for increased noise immunity the two buses are separately buffered. vbulk istart-up vcc vself-supply vdrain t t t t t 4. 5 ma 14.5 v 4 0v
AN1261 application note 6/28 figure 6. high-voltage start-up generator figure 7. l6590 internal supply architecture under uvlo conditions the consumption of the ic, mainly due to the uvlo block and the bandgap generator, is below 1ma and this current is supplied by the internal start-up generator. when the device is running the consumption is obviously higher. at v cc = 10v the consumption, driver not in- cluded, is about 3.6ma (typ.). the consumption of the driver depends on which frequency the oscillator is set at: it is typically 0.2ma at low frequency and 0.5ma at high frequency, for a total consumption of 4.1ma maxi- mum, that is 41mw. power mosfet and gate driver the power switch is implemented with a lateral n-channel dmos having a v (br)dss of 700v min. and a typical r ds(on) of 13 w . it has a sensefet structure to allow a virtually lossless current sensing (used only for protec- tion). during operation in discontinuous conduction mode at low mains the drain voltage is likely to go below ground. 17 v drain vcc 15 m w uvlo 150 w gnd power mosfet vcc uvlo bandgap generator 2.5v to e/a of l6590/l6590d driver analog circuits digital circuits linear regulator
7/28 AN1261 application note any risk of injecting the substrate of the ic on such occurrence is prevented by an internal structure surrounding the ndmos. the gate driver of the power mosfet is designed to supply a controlled gate current during both turn-on and turn-off in order to minimize common mode emi. under uvlo conditions an internal pull-down circuit, shown in figure 8, holds the gate low in order to ensure that the power mosfet cannot be turned on accidentally. when the device is turned on the uvlo signal is pulled high (refer to figure 8) and the circuit is disabled. figure 8. gate pull-down during uvlo oscillator and pwm control pwm regulation is accomplished by implementing voltage mode control. as shown in fig. 9, this block includes an oscillator, a pwm comparator, a pwm latch and, in the l6590 and l6590d, an error amplifier as well. figure 9. pwm control block vcc uvlo drain driver uvlo pull_down power mosfet clock + - from ocp comparator comp s r q max. duty cycle oscillator to gate driver vfb pwm 2.5 v + - e/a l6590a clock + - from ocp comparator comp s r q max. duty cycle oscillator to gate driver pwm 1ma l6590
AN1261 application note 8/28 the oscillator generates three signals: a clock pulse train to set the pwm latch, a triangular sawtooth applied to the (+) input of the pwm modulator and a square wave with 70% duty cycle used to gate the output of the pwm latch and set the maximum duty cycle of the power switch. the oscillator operates at a frequency internally fixed at 65 khz with a precision of 10%. this value has been selected so that the second harmonic falls below 150khz, beyond which some international emc standards en- visage more severe limits. the oscillator is implemented by means of two current generators trimmed and temperature compensated (see fig. 10). figure 10. oscillator internal schematic figure 11. voltage mode control pwm timing diagram 5v bus qr qs 3.5 v 1.5 v 3i 7i - + + - c t to pwm comparator maximum duty cycle clock d dt c t v comp max duty clock (s) pwm ou t r ocp gate drive drain current normal operation overload zero load skipped cycle overcurrent threshold minimum on-time propagation delay t t t t t t t t 15 m s45 m s
9/28 AN1261 application note they alternately charge and discharge an internal capacitor c t between two voltage levels (1.5v and 3.5v) thus generating a triangular waveform. to achieve 70% duty cycle the charge and discharge currents are in a 3:7 ratio. the gating signal to set the maximum duty cycle is taken from the q output of the rs latch, while the clock pulse is generated during the low-high transition of the output q. the pwm latch (reset dominant) is set by the clock pulses of the oscillator and is reset by either the pwm com- parator or the overcurrent comparator (ocp, see oprotectionso section). the error amplifier (e/a) of the l6590 and l6590d is an op-amp with a mos input stage and a class ab output stage. the amplifier is compensated for closed loop stability at unity gain, has a small-signal dc gain of 70db (typ.) and a gain-bandwidth product over 1 mhz. the output of the e/a is fed to the inverting input of the pwm comparator and is externally available at pin 4 (comp) for frequency compensation. since this voltage controls the duty cycle, it will be referred to as the ocontrol voltageo. in the l6590a the inverting input of the pwm comparator, that is the control voltage, is externally available at pin 4 (comp) in order for an optocoupler-based circuit to modulate its voltage, so as to close the control loop that regulates the converter's output voltage. the operation of this voltage mode control loop is illustrated in fig. 11. a clock pulse from the oscillator sets the pwm latch, which drives high the gate driver, and the power mosfet is switched on. the voltage on c t ramps up and, as it hits the level at the inverting input, the pwm comparator reverses and resets the pwm latch terminating the conduction of the power mosfet. the voltage on c t completes its ramp- up, after that it starts ramping down until the valley is reached. then another clock pulse is released and another cycle begins. in case of overcurrent the control voltage saturates high and the conduction of the power mosfet is stopped by the ocp comparator instead of the pwm comparator. at very light load the control voltage is close to its low saturation and the gate drive delivers as short pulses as it can, bottom limited by internal delays. they are how- ever too long to maintain the long-term energy balance, thus from time to time some cycles need to be skipped and the operation becomes asynchronous. this is automatically done by the control loop: if there is a short-term excess of energy the control voltage saturates low completely and the reset signal is still high while the set clock pulse is released by the oscillator. being the pwm latch reset dominant, the power mosfet will not be turned on in that cycle. standby function the standby function, optimized for flyback topology, automatically detects a light load condition for the convert- er and decreases the oscillator frequency on that occurrence. the normal oscillation frequency is automatically resumed when the output load builds up and exceeds a defined threshold. this function allows to minimize power losses related to switching frequency, which represent the majority of losses in a lightly loaded flyback, without giving up the advantages of a higher switching frequency at heavy load. a positive side effect is a smooth transition from fixed frequency to asynchronous operation, as described in the previous section, when the load decays to very low values and approaches zero. the standby function is realized by monitoring the peak current in the power switch, being this related to the input power (see ref. [1] for details). if the peak primary current decreases below a fixed threshold (80 ma) as a result of a reduced power demanded by the load, the oscillator frequency will be set at a lower value (22 khz). this is done by dividing by three the capability of the current generators shown in fig. 10. when the load demands more power, the peak primary current increases and exceeds a second threshold (190ma): then the oscillator frequency is reset at the normal value (65khz). this 110ma hysteresis prevents undesired frequency change when power is such that the peak current is close to the threshold.
AN1261 application note 10/28 figure 12. standby function timing diagram pout peak primary current 2ms 1ms standby (filtered) 190 ma 80 ma f sw 65 khz 22 khz standby (before filter) vout load regulation small glitch the signal coming from the sense circuit is digitally filtered to avoid false triggering of this function as a result of large load changes or noise. the filtering time is about 2 ms during the transition high-low and about 1 ms during the transition low-high. figure 12 illustrates the operation of the function. the effect of the frequency change to the converter's output voltage is a few mv glitch, much smaller than the overshoots and the undershoots resulting from a step load change. the effect of the frequency reduction in terms of input power saving and efficiency increase (for a given load) is shown in fig. 13, with reference to the 10w test-board (2) shown in the datasheet of the l6590. the effect would be much more pronounced if rc snubbers were to be used on the secondary rectifi- er(s) or on the primary side to comply with emi re- quirements. figure 13. power saving and efficiency rise due to the standby function brownout protection (l6590a and l6590d only) brownout protection is basically a not-latched device shutdown functionality whose typical use is to sense a mains undervoltage. nevertheless, this function d dh 50 100 150 200 250 300 350 400 vin [v] 0 0.05 0.1 0.15 0.2 pin [w] 1 2 3 4 5 [%] pout = 1 w d pin dh d pin = pin @ 65 khz - pi n @ 22 khz dh = h @ 65 khz - h @ 22 khz
11/28 AN1261 application note can serve other purposes as well, as shown in the section oapplication ideaso, figure 20. there are several reasons why it may be desirable to shut down a converter during brownout conditions, that is when the mains voltage falls below the minimum specification of normal operation. one of these is that a brownout condition may cause overheating of the primary power section due to an excess of rms current. although this does not concern the ic directly since it is thermally protected (see the section othermal shutdowno), however this might be a problem in an smps including two converters (a high-power main converter and a low-power one for housekeeping and/or standby operation), such as in pc's silver boxes. if either the l6590a or l6590d is used for the auxiliary converter and powers the controller of the main converter as well, the latter could benefit from shutdown in case of brownout. brownout can also cause a converter to work open-loop and this could be dangerous to the converter itself and the load, should the input voltage return abruptly to its rated value. another problem is the spurious restarts that are likely to occur during converter power down if the input voltage decays slowly (e.g. with a large input bulk capacitor) and that cause the output voltage not to decay to zero monotonically. figure 14. brownout protection internal circuit and timing diagram converter shutdown can be accomplished with the l6590a or the l6590d by means of an internal comparator that can be used to sense the input voltage downstream the bridge rectifier, across the input bulk capacitor. this comparator is internally referenced to 2.5v and disables the pwm if the voltage applied at its externally available (non-inverting) input is below the internal reference, as shown in fig. 14. pwm operation is re-enabled as the voltage at the non-inverting input is more than 2.5v. the brownout comparator is provided with current hysteresis instead of a more usual voltage hysteresis: an in- ternal 50 m a current generator is on as long as the voltage applied at the non-inverting input exceeds 2.5v and is off if the voltage is below 2.5v. this approach provides an additional degree of freedom: it is possible to set the on threshold and the off threshold separately by properly choosing the resistors of the external divider (see below). with voltage hyster- hv input bus vinok vcc v on v off pwm vout + - l6590d l6590a 2.5 v vinok 50 m a hv input bus 6.4 v bok vcc
AN1261 application note 12/28 esis, instead, fixing one threshold automatically fixes the other one depending on the built-in hysteresis of the comparator. the following relationships can be established for the on (v inon ) and off (v inoff ) thresholds of the input volt- age: ;, which, solved for r1 and r2, yield: ;. for a proper operation of this function, v inon must be less than the peak voltage at minimum mains and v inoff less than the valley voltage on the input bulk capacitor at minimum mains and maximum load. while the brownout protection is active the start-up generator keeps on working but there is no pwm activity, thus the v cc voltage continuously oscillates between the start-up and the uvlo thresholds, as shown in the timing diagram of fig. 14. the bok pin is a high impedance point connected to high value resistors, thus it is prone to pick up noise. this might alter the off threshold when the converter is running or give origin to undesired switch-off of the ic during esd tests. a film capacitor (e.g. 1-100 nf) can be connected in parallel to r2 to prevent any malfunctioning of this kind. if the function is not used the pin can be left floating: a small internal pull-up generator ( 5 m a, not shown in fig. 14 for simplicity) maintains the voltage high and lets the device run normally. for more noise im- munity the pin can be connected to v cc through a 15 k w resistor. overvoltage protection the devices of the l6590 family incorporate an overvoltage protection (ovp) that can be particularly useful to protect the converter and the load against voltage feedback loop failures. this kind of failure causes the output voltage to rise with no control and easily leads to the destruction or damage of the load and of the converter itself if not properly handled. if such an event occurs, the voltage generated by the auxiliary winding that supplies the ic will fly up tracking the output voltage. an internal comparator (see figure 15) continuously monitors the v cc voltage and stops the operation of the ic if the voltage exceeds a threshold. this condition is latched and maintained until the v cc voltage falls below the uvlo threshold. the converter will then operate intermittently. figure 15. ovp circuit v inon r2 r1 r2 + ---------------------- ? 2.5 = v inoff 2.5 r1 --------------------------------- 50 10 6 ? + 2.5 r2 ------- - = r1 v inon v inoff 50 10 6 ? ----------------------------------------- = r2 r1 2.5 v inon 2.5 ------------------------------ ? = vcc drain + - to ovp latch gnd to mosfet ovp
13/28 AN1261 application note such kind of operation may also occur when the converter is overloaded because of the large spikes on the positive-going edges of the voltage delivered by the self-supply winding. these spikes may charge the v cc ca- pacitor to an abnormal value and trigger the ovp comparator. this will help reduce the power throughput and the stress on the secondary rectifier(s). overcurrent protection the devices use pulse-by-pulse current limiting for overcurrent protection (ocp), not to overstress of the inter- nal mosfet: its current during the on-time is monitored and, if exceeding a determined value, the conduction is terminated immediately. the mosfet will be turned on again in the subsequent switching cycle. as previously mentioned, the mosfet has a sensefet structure: the source of a few cells are connected to- gether and kept separate from the other source connections, to realize a 1:100 current divider. the osenseo por- tion is connected to a 75 w ground referenced sense resistor r sense having a low thermal coefficient (the resistance drift is less than 3% over the operating temperature range). as shown in fig. 16, the ocp comparator senses the voltage drop across rsense and resets the pwm latch (thus turning off the mosfet) if the drop exceeds a threshold set at 0.5v (this value is trimmed to get an overall precision of 10%). in this way the over- current limit will be set at ilim = (0.5v/75 w )*100 0.65a (typical value). to increase noise immunity, the output of the ocp comparator is blanked for a short time (about 120 ns) just after the mosfet is turned on, so that any disturbance within the blanking time is rejected. this is what is com- monly known as leb (leading edge blanking). this blanking time adds up to other internal delays in the control loop path giving origin to the total propagation delay shown in fig. 11, which has an impact on the ocp charac- teristics as a function of the current slope. figure 16. ocp circuit internal schematic thermal shutdown overheating of the device due to an excessi ve power throughput or insufficient heatsink ing is avoided by the thermal shutdown function. a thermal sensor monitors the junction temperature clos e to the power mosfet and, when the temperature exceeds 150 c (min.), sets an alarm signal that stops the operation of the device. there is no more pwm activity but the start-up generator keeps on working, thus the v cc voltage continuously oscillates between the start- up and the uvlo thresholds. this behaviour is identical to the one shown in fig. 14, resulting from the brownout pro- tection. in these conditions, the device's quiesc ent current is reduced at less than 1ma. this is a not-latched function and the power mosfet is re-enabled as the chip temperature falls about 40 c. clock + - drain gnd 1 1/100 s r q max. duty cycle oscillator pwm driver rsense ocp + - 0.5 v leb clock
AN1261 application note 14/28 application information application ideas the following schematics show a few simple circuits able to solve some common application issues that can be encountered during the implementation of converters based on the l6590 family devices. figure 17. protection against overload, short circuit or open feedback: a) hiccup mode; b) latch mode figure 18. mains ovp (the values shown set the threshold at 412v) figure 19. leb circuit for leakage inductance spikes filtering, to improve primary regulation. comp 33 k w 1 10 m f bc337 1k w bc327 l6590 l6590d l6590a 5.1 to 7.5 k w a) b) comp 33 k w 1 10 m f bc337 bc327 l6590 l6590d l6590a 5.1 to 7.5 k w vcc 1k w 1n4148 47 w vcc r l 22 k w bc337 l6590 l6590d vfb r h 3m w hv input bus 4.7 nf v ovp =3 r h r l r e 2k w vcc gnd l6590 l6590d l6590a 1n4148 bc327 10 k w 100 pf 22 m f
15/28 AN1261 application note figure 20. simple secondary feedback figure 21. secondary feedback with floating optocoupler (l6590, l6590d) figure 22. secondary feedback with floating optocouler (l6590a) vout vz+1 vz l6590 l6590d l6590a comp i f i c vfb 10 100 nf r b vout 20i f not needed in l6590a r bb 220 w (for vout<10v) l6590 l6590d vcc n aux r h2 r l2 r f2 vfb comp c f2 r c i c 470 nf cs tl431 vout r b r h1 r l1 c f1 v k i f r f1 l6590a vcc n aux r h2 r l2 comp r c i c 470 nf cs tl431 vout r b r h1 r l1 c f1 v k i f r f1 470 w c comp
AN1261 application note 16/28 figure 23. primary feedback with the l6590a figure 24. compensation of voltage drop on long wires figure 25. thermal protection l6590a comp c comp 1n4148 470 w 1k w vcc bc337 vz (12 to 15v) 22 m f rs vout (vz + v f +1) ns naux -v f iout [a] [v] vout and vload vs. iout vout vload r k =r z r2 r1 r b r1 r2 tl431 c f1 v k rload vload vout r z r k vload = 2.5 ( 1+ ) r1 r2 2. 5v r f1 l6590d l6590a vcc bok ptc l6590d l6590a vcc bok ntc
17/28 AN1261 application note the circuits of figure 17 can be used for reduction of the power throughput of the converter (a), or for stopping it completely (b), in case of overload, short circuit or feedback disconnection. circuit a) pulls the output of the error amplifier to ground if this saturates high and stays latched. the pwm is stopped and the converter remains idle until the v cc voltage goes below the uvlo threshold, after that the latch turns off and the device is started again. the result is an intermittent operation that reduces the power through- put significantly (ohiccupo mode operation). a delay is provided to avoid improper activation at start-up. circuit b) works the same way but pulls low the supply voltage of the ic too. the latch is kept alive by the internal start-up generator, hence it is necessary to disconnect the input source to restart the converter. figure 18 shows how to implement a mains overvoltage protection. the system offers a precision better than 5% since it uses the precise internal reference as a pedestal, so that the variations of the bjt threshold have a limited impact. shutdown is not immediate, the output voltage is reduced progressively as the threshold is ap- proached. for a sharper intervention use lower r l ,r h values or higher r e values. note that in not-isolated or primary regulated configurations r e is the low-side resistor of the divider that sets the output voltage. figure 19 shows a leb (leading edge blanking) circuit that blanks the spike (due to the transformer's leakage inductance) appearing at the rising edges of the voltage generated by the self-supply winding. this reduces the influence of the converter's load on the v cc voltage. in a system with secondary feedback v cc will drift less, in case of primary feedback load regulation will be improved considerably. figure 26. remote on/off control figure 27. soft-start l6590 l6590d comp on off 10 k w 10 k w bc337 l6590d l6590a vcc on off 10 k w 10 k w bc337 bok 15 k w vout r b r h1 r l1 tl431 c f1 c ss 1to47 m f r d r f1
AN1261 application note 18/28 figure 20 shows a very simple type of secondary feedback that can be used when the tolerance required on the output voltage, although not so tight as to require a precise secondary reference, is too stringent for primary feedback (e.g. because there is a very large load range). the resulting tolerance depends mainly on the zener voltage spread and its temperature variation. in figure 21 an alternative connection of the phototransistor is shown. it is useful to achieve hiccup mode oper- ation in case of overload or short circuit. it is useful also when the supply voltage of the ic experiences a very large variation (e.g. in battery chargers). the ic's ovp protection is bypassed by such configuration, but if the optocoupler failes the phototransistor will no longer be able to supply the ic, which will go into uvlo just like in case of overload or short circuit. figure 22 illustrates the circuit of figure 21 adapted to the l6590a, which is not provided with an e/a. figure 23 shows how to make a primary sensing feedback with the l6590a (which is not provided with an e/a) in converters where load regulation is not a concern. in figure 24 it is shown how to arrange the feedback loop on the secondary side to achieve a perfect voltage regulation on the load when this is connected to the converter's output with a long cable, provided the total re- sistance rz of the cable is known. this can be useful in ac-dc adapters. figure 25 shows a different use of the bok pin: the thermal protection of a power component besides the ic, for instance the transformer or a secondary rectifier. the first solution (with an ntc) is preferred with primary regulation because vcc is fixed by the feedback and the temperature threshold is then tightly determined. the second one is preferred in secondary regulation because vcc may vary, thus precision is given by the abrupt change of the ptc resistance value at its critical temperature. figure 26 shows two possible solutions to turn on and off the device by means of a logic signal, while figure 27 gives a clue on how to realize soft-start to avoid excessive inrush current at start-up. c ss is connected to a low impedance point, thus it has little effect on the feedback loop compensation. r d is used for discharging c ss when the converter is powered off.
19/28 AN1261 application note application examples here follows a series of example circuits aimed at covering the most common applications that the l6590 family can address. figure 28. 10w ac-dc adapter with primary feedback (l6590 and l6590d) figure 29. not-isolated 10w ac-dc adapter (l6590 and l6590d) c2 22 m f 25 v c4 100 nf c7, c8 330 m f 16 v d1 bzw06-154 d3 1n4148 d4 stps3l60s ic1 c9 100 m f 16 v r1 100 w r4 1k w d2 stta106 l1 4.7 m h t1 c1 22 m f 400 v c6 2.2 nf y c5 2.2 nf bd1 d f06m vin 88 to 264 vac f1 2a/250v l 22 mh cx a 100 nf cx b 100 nf r2 3.9 k w r3 27 k w t1 specification core e20/10/6, ferrite 3c85 or n67 or equivalent 0.5 mm gap for a primary inductance of 1.6 mh l leakage <30 m h primary : 130 t, 2 series windings 65t each, awg33 ( ? 0.22 mm) sec : 14 t, awg26 ( ? 0.4 mm) aux : 14 t, awg33 vo =12 v 10% po= 1 to 10 w 3 (4) 1 5 (8) 4 (7) 6, 7, 8 (9 to 16) l6590 (l6590d) t1 specification core e20/10/6, ferrite 3c85 or n67 or equivalent 0.5 mm gap for a primary inductance of 1.6 mh l leakage <30 m h primary : 130 t, 2 series windings 65t each, awg33 ( ? 0.22 mm) sec : 14 t, awg26 ( ? 0.4 mm) vo =12 v 3% io= 0 to 0.8 a c2 22 m f 25 v c4 100 nf c7, c8 330 m f 16 v d1 bzw06-154 d3 1n4148 d4 stps 3l60s ic1 c9 100 m f 16 v r1 10 w r4 1k w d2 stta106 l1 4.7 m h t1 c1 22 m f 400 v c5 2.2 nf bd1 d f06m vin 88 to 264 vac f1 2a/250v l 22 mh cx a 100 nf cx b 100 nf r2 3.9 k w r3 27 k w 3 (4) 1 5 (8) 4 (7) 6, 7, 8 (9 to 16) l6590 (l6590d)
AN1261 application note 20/28 figure 30. 15w auxiliary smps for pc (l6590d) figure 31. 7w battery charger (l6590 and l6590d) t1 specification core e20/10/6, ferrite 3c85 or n67 or equivalent 0.9 mm gap for a primary inductance of 2 mh l leakage <50 m h primary : 200 t, 2 series windings 100t each, awg33 ( ? 0.22 mm) sec : 9 t, 2 x awg23 ( ? 0.64 mm) aux : 21 t, awg33 4 1 67 9, ..., 16 5 vdc / 3 a c2 22 m f 25 v c8 100 m f 10v d1 bzw06-154 d3 1n4148 d4 stps10l25d op1 pc817 l6590d ic1 3 4 1 2 3 c5, c6, c7 470 m f 10 v r1 10 w c3 47 nf l1 4.7 m h t1 d2 stta106 c9 470 nf 2 1 ic2 tl431 vin = 200 to 375 vdc r2 1.8 m w r3 20 k w c1 10 nf c4 2.2 nf y r4 560 w r5 2.43 k w r6 2.43 k w 5 r7 240 w 8 t1 sp ecification core e20/10/6, ferrite 3c85 or n67 or equivalent 1 mm gap for a primar y inductance of 2.6 mh l leak age <60 m h primary : 230 t, 2 series windings 115t each, awg36 ( ? 0.16 mm) sec : 13 t, awg23 ( ? 0.64 mm) aux : 60 t, awg36 7.2 vdc / 1 a c3 10 m f 25v c4 2.2 nf y1 class c8 680 nf d1 bzw06-154 d3 bav21 d4 1n5821 op1 pc817 c5, c6 330 m f 16v r1 39 w c3 10 nf t1 16:1 d2 stta106 bd1 df06m vin 88 to 264 vac f1 2a/250v l 22 mh cx a 100 nf cx b 100 nf c1 22 m f 400 v r9 22.6 k w r13 12 k w c2 220 nf r2 5.6 k w r3 1.5 k w r4 10 k w 1 2 ic2 tsm103 3 8 4 2 1 d5 1n4148 d6 1n4148 d7 1n4148 d8 bzx79c12 c7 10 m f 25v c9 330 nf r5 4.7 k w 4 3 r6 0.1 w r10 6.8 k w r7 620 w r11 11.8 k w r8 560 w r12 1k w 7 6 5 q1 bc337 3 (4) 1 4 (7) 5 (8) 6, 7, 8 (9 to 16) l6590 (l6590d)
21/28 AN1261 application note figure 32. 15w auxiliary smps for pc (l6590a) figure 33. simple 10w ac-dc adapter with brownout protection (l6590a and l6590d) t1 specification core e20/10/6, ferrite 3c85 or n67 or equivalent 0.9 mm gap for a primary inductance of 2 mh l leakage <50 m h primary : 200 t, 2 series windings 100t each, awg33 ( ? 0.22 mm) sec : 9 t, 2 x awg23 ( ? 0.64 mm) aux : 21 t, awg33 3 1 54 6, 7, 8 5 vdc / 3 a c2 22 m f 25 v c8 100 m f 10v d1 bzw06-154 d3 1n4148 d4 stps10l25d op1 pc817 l6590a ic1 4 3 1 2 3 c5, c6, c7 470 m f 10 v r1 10 w c3 47 nf l1 4.7 m h t1 d2 stta106 c9 470 nf 2 1 ic2 tl431 vin = 200 to 375 vdc r2 1.8 m w r3 20 k w c1 10 nf c4 2.2 nf y r4 560 w r5 2.43 k w r6 2.43 k w r7 240 w t1 specification core e20/10/6, ferrite 3c85 or n67 or equivalent 0.5 mm gap for a primary inductance of 1.6 mh l leakage <30 m h primary : 130 t, 2 series windings 65t each, awg33 ( ? 0.22 mm) sec : 14 t,awg26 ( ? 0.4 mm) aux : 14 t, awg33 3 (4) 1 5 (6) 4 (7) 6, 7, 8 (9 to 16) c2 22 m f 25 v d1 bzw06-154 d3 1n4148 op1 pc8 17 l6590a (l6590d) ic1 4 3 1 2 r1 10 w c4 47 nf t1 d2 stta106 d5 bzx79c10 r2 1.8 m w r3 39 k w c3 10 nf c5 2.2 nf y r4 100 w 12 vdc / 0.8 a c6, c7 330 m f 16 v d4 stps3l60s c8 100 m f 16 v l1 4.7 m h r5 1k w bd1 df06m vin 88 to 264 vac f1 2a/250v l 22 mh cx a 100 nf cx b 100 nf c1 22 m f 400 v (8)
AN1261 application note 22/28 figure 34. non-isolated 5.5w, european mains smps for plm miscellaneous topologies the following schematics show some topologies other than flyback that can be approached with the devices of the l6590 family. figure 35. forward converter 3 1 5 4 6, 7, 8 12 vdc 10% 0.4 a c4 22 m f 25 v c5 680 nf c10 470 m f 16 v r6 18 k w d2 bzw06-213 d4 1n4148 d5 1n5819 l6590 ic1 r8 75 k w r7 2k w d3 stta106 l4 10 m h t1 vinac 180 to 270 v f1 tr5-f 0.25a r10 2.2 k w c6 10 nf c2,c3 10 m f 400v c11 470 m f 16 v l3 10 m h 5vdc 5% 0.1 a r2 1m w r3 1m w r5 22 k w q1 bc337 r9 2.2 k w c8 470 m f 16 v c9 470 m f 16 v r4 1m w d6 1n5819 c7 4.7nf l1 68 m h r1 39 w l2 1mh c1 100 nf x2 d1 1n4005 notch filter to plm line connection t1 specification core e16/8/5, ferrite 3c85 or n67 or equivalent 0.5 mm gap for a primary inductance of 0.7 mh l leakage <20 m h primary : n1 = 100 t, 2 series windings 50t each, awg33 ( ? 0.22 mm) sec1 : n2 = 8 t, 2xawg26 ( ? 0.4 mm) sec2 : n3 = 5 t, 2xawg26 n2 n3 n1 3 1 5 4 6, 7, 8 vout l6590 vin
23/28 AN1261 application note figure 36. boost converter figure 37. voltage-boosted boost converter 3 1 5 4 6, 7, 8 l6590 vin vout 3 1 5 4 6, 7, 8 l6590 vin vout
AN1261 application note 24/28 figure 38. current-boosted boost converter figure 39. positive buck converter figure 40. negative buck converter 3 1 5 4 6, 7, 8 l6590 vin vout vout > 8 v 3 1 5 4 6, 7, 8 l6590 vin vout needed for vout > 16v vout 3 1 5 4 6, 7, 8 l6590 vin vout < 8v 3 1 5 4 6, 7, 8 l6590 -vin -vout |vin| - |vout| < 8 |vin| - |vout| > 8 v 3 1 5 4 6, 7, 8 l6590 -vin -vout needed for |vin| - |vout| >16 v
25/28 AN1261 application note figure 41. positive-to-negative buck-boost converter figure 42. negative-to-positive buck-boost converter figure 43. cascaded-flyback converter 3 1 5 4 6, 7, 8 l6590 vin -vout vout > -8 v vout < -8 v 3 1 5 4 6, 7, 8 l6590 -vout vin needed for vout < -16 v |vin| - |vout| < 8 v 3 1 5 4 6, 7, 8 l6590 -vin vout |vin| - |vout| > 8 v 3 1 5 4 6, 7, 8 l6590 -vin vout needed for |vin| - |vout| > 16v 3 1 5 4 6, 7, 8 l6590 vout vin vout < 8 v 3 1 5 4 6, 7, 8 l6590 vout vin vout > 8 v needed for vout > 16 v
AN1261 application note 26/28 figure 44. sepic converter figure 45. c?k converter the forward converter of fig. 35 can use a smaller core than flyback because it does not store energy. this topology is suitable for generating low voltage, high current isolated output. the boost converter of fig. 36 provides an output voltage higher than the input voltage with no isolation. the maximum output voltage is limited at below 700v by the breakdown of the internal mosfet and the maximum output-to-input voltage ratio cannot exceed 3.3 due to the maximum duty cycle of 70%. the voltage-boosted boost converter of fig. 37 uses a tapped inductor to get an output voltage higher than the standard boost converter. the price to pay for that is a reduced power capability. a clamp should be added to the drain pin to limit spikes due to the leakage inductance. the current-boosted boost converter shown in fig. 38 uses a tapped inductor to increase the output power sig- nificantly, compared to the standard boost. the price to pay is an increased peak drain voltage thus this con- figuration can be used if the output voltage is not too high. also here a clamp should be added to the drain pin to limit spikes due to the leakage inductance. the positive buck converters in fig. 39 step a positive input voltage down to a lower output voltage. they use a special configuration with the ground pin of the device floating. this requires a bootstrapped supply voltage, thus a minimum load is required for a proper start-up and operation. also the feedback is delivered with a bootstrap technique. vout > 8 v 3 1 5 4 6, 7, 8 l6590 vin vout needed for vout >16v vout < 8v 3 1 5 4 6, 7, 8 l6590 vin vout 3 1 5 4 6, 7, 8 l6590 vin -vout
27/28 AN1261 application note the negative buck converters shown in fig. 40 step a negative input voltage down to a lower (absolute value) negative output voltage. the feedback uses a pnp as a level shifter and the optional diode and resistor can be used to compensate the temperature variation of v be . the positive-to-negative buck-boost converter in fig. 41 is a variant of the positive step-down of fig. 39 to gen- erate a negative output from a positive input voltage. it can work as either step-up or step-down and requires a minimum load for a proper start-up and operation. the negative-to-positive buck-boost converter in fig. 42 is instead a variant of the negative step-down of fig. 40 to generate a positive output from a negative input voltage. it can work as either step-up or step-down and re- quires a minimum load for a proper start-up and operation. the cascaded flyback converters of fig. 43 work as a step-down and are useful for low power applications when isolation is not required and the input-to-output voltage ratio is very high. in fact it does not require as narrow duty cycles as the buck configuration does. the power capability attainable is however quite low. figures 44 and 45 show a sepic and a c?k converter respectively. both converters can be either step-down or step-up. the c?k converter delivers a negative voltage, thus an additional winding is needed in any case for supplying the ic. besides, the feedback uses a current mirror, as well as an npn as a level shifter. the optional diode and resistor can be used to compensate the temperature variation of v be for the npn. reference [1] ominimize power losses in a lightly loaded flyback converter with the l5991 pwm controllero (an1049) [2] ooffline flyback converters design methodology with the l6590 familyo (an1262)
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http:/ /www.st.com 28/28 AN1261 application note

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